Related
dkn37 I'm writing a static pattern rule to generate a list of dependencies for targets matching the pattern. Dependencies are generated via shell commands (file contents provide information about dependencies). Here is an example of an explicit rule: f1.o: $(s
dkn37 I'm writing a static pattern rule to generate a list of dependencies for targets matching the pattern. Dependencies are generated via shell commands (file contents provide information about dependencies). Here is an example of an explicit rule: f1.o: $(s
Turamba I am trying to append some text to a file from inside a make target using the following syntax $shell(echo "module load ABC/$$(MODULE_LOAD)" >> $@/_env/local/filexyz)
But GNU Make 4.2.1 complains about the following. /bin/sh: -c: line 21: syntax error
Turamba I am trying to append some text to a file from inside a make target using the following syntax $shell(echo "module load ABC/$$(MODULE_LOAD)" >> $@/_env/local/filexyz)
But GNU Make 4.2.1 complains about the following. /bin/sh: -c: line 21: syntax error
Jim Moriarty I am new to makefiles. I am trying to perform some shell operations in a makefile under a target. I created a new_target without modifying working code. The code looks like this: all: new_target existing_target
new_target:
TEST_FILES:=$(
sebastian_t I have a Makefile that defines a docker-compose project. Essentially it's one of my commands: COMMAND := docker-compose --project-name=$(PREFIX) --file=$(FILE_PATH)
up:
$(COMMAND) up -d
I want to add a targetname to which dcI can pass any par
sebastian_t I have a Makefile that defines a docker-compose project. Essentially it's one of my commands: COMMAND := docker-compose --project-name=$(PREFIX) --file=$(FILE_PATH)
up:
$(COMMAND) up -d
I want to add a targetname to which dcI can pass any par
sebastian_t I have a Makefile that defines a docker-compose project. Essentially it's one of my commands: COMMAND := docker-compose --project-name=$(PREFIX) --file=$(FILE_PATH)
up:
$(COMMAND) up -d
I want to add a targetname to which dcI can pass any par
Ivan Gabriele: I'm from NodeJS land, so I think of Makefiles as the "scripts" section in npm package.json, which might be wrong (or not?). So my idea is to automate repetitive actions when installing new dependencies by typing: make install github.com/stretchr
Ivan Gabriele: I'm from NodeJS land, so I think of Makefiles as the "scripts" section in npm package.json, which might be wrong (or not?). So my idea is to automate repetitive actions when installing new dependencies by typing: make install github.com/stretchr
Ivan Gabriele: I'm from NodeJS land, so I think of Makefiles as the "scripts" section in npm package.json, which might be wrong (or not?). So my idea is to automate repetitive actions when installing new dependencies by typing: make install github.com/stretchr
Ivan Gabriele: I'm from NodeJS land, so I think of Makefiles as the "scripts" section in npm package.json, which might be wrong (or not?). So my idea is to automate repetitive actions when installing new dependencies by typing: make install github.com/stretchr
Kenorb Mine Makefileare: .PHONY: check
check:
ifneq $(shell echo 123), $(shell echo 123)
$(error Not equal)
endif
When I run, I get the error: $ make
Makefile:3: *** Not equal. Stop.
However, this should only happen if they a
red 888 ❯ make --version
GNU Make 3.81
❯ bash --version
GNU bash, version 3.2.57(1)-release (x86_64-apple-darwin18)
How can I pass a variable to $(shell) from inside a for loop? I can access the var outside of $(shell), but I don't know how to pass it to A_L
Kenorb Mine Makefileare: .PHONY: check
check:
ifneq $(shell echo 123), $(shell echo 123)
$(error Not equal)
endif
When I run, I get the error: $ make
Makefile:3: *** Not equal. Stop.
However, this should only happen if they a
Kenorb Mine Makefileare: .PHONY: check
check:
ifneq $(shell echo 123), $(shell echo 123)
$(error Not equal)
endif
When I run, I get the error: $ make
Makefile:3: *** Not equal. Stop.
However, this should only happen if they a
user 541686 when i run export PATH := mypath
$(error $(shell echo "$${PATH}"))
Nothing seems to PATHchange for my call shell. Why is this happening and how do I actually change the PATHfor shellcall? Florian Weimer Is this GNU make? There's a long-standing GN
red 888 ❯ make --version
GNU Make 3.81
❯ bash --version
GNU bash, version 3.2.57(1)-release (x86_64-apple-darwin18)
How can I pass a variable to $(shell) from inside a for loop? I can access the var outside of $(shell), but I don't know how to pass it to A_L
w I have a GNU makefile . It runs fine on Linux, Solaris and OS X. However, under Cygwin-32, Cygwin-64 and MinGW it produces: /bin/sh: -c: line 0: syntax error near unexpected token `('
/bin/sh: -c: line 0: `echo 2.0.4(0.287/5/3) | egrep -i -c "fc22.i686"'
Th
red 888 ❯ make --version
GNU Make 3.81
❯ bash --version
GNU bash, version 3.2.57(1)-release (x86_64-apple-darwin18)
How can I pass a variable to $(shell) from inside a for loop? I can access the var outside of $(shell), but I don't know how to pass it to A_L
red 888 ❯ make --version
GNU Make 3.81
❯ bash --version
GNU bash, version 3.2.57(1)-release (x86_64-apple-darwin18)
How can I pass a variable to $(shell) from inside a for loop? I can access the var outside of $(shell), but I don't know how to pass it to A_L
red 888 ❯ make --version
GNU Make 3.81
❯ bash --version
GNU bash, version 3.2.57(1)-release (x86_64-apple-darwin18)
How can I pass a variable to $(shell) from inside a for loop? I can access the var outside of $(shell), but I don't know how to pass it to A_L
Kenorb Mine Makefileare: .PHONY: check
check:
ifneq $(shell echo 123), $(shell echo 123)
$(error Not equal)
endif
When I run, I get the error: $ make
Makefile:3: *** Not equal. Stop.
However, this should only happen if they a
Kenorb Mine Makefileare: .PHONY: check
check:
ifneq $(shell echo 123), $(shell echo 123)
$(error Not equal)
endif
When I run, I get the error: $ make
Makefile:3: *** Not equal. Stop.
However, this should only happen if they a
Kenorb Mine Makefileare: .PHONY: check
check:
ifneq $(shell echo 123), $(shell echo 123)
$(error Not equal)
endif
When I run, I get the error: $ make
Makefile:3: *** Not equal. Stop.
However, this should only happen if they a
Kenorb Mine Makefileare: .PHONY: check
check:
ifneq $(shell echo 123), $(shell echo 123)
$(error Not equal)
endif
When I run, I get the error: $ make
Makefile:3: *** Not equal. Stop.
However, this should only happen if they a
user 541686 when i run export PATH := mypath
$(error $(shell echo "$${PATH}"))
Nothing seems to PATHchange for my call shell. Why is this happening and how do I actually change the PATHfor shellcall? Florian Weimer Is this GNU make? There's a long-standing GN
red 888 ❯ make --version
GNU Make 3.81
❯ bash --version
GNU bash, version 3.2.57(1)-release (x86_64-apple-darwin18)
How can I pass a variable to $(shell) from inside a for loop? I can access the var outside of $(shell), but I don't know how to pass it to A_L
red 888 ❯ make --version
GNU Make 3.81
❯ bash --version
GNU bash, version 3.2.57(1)-release (x86_64-apple-darwin18)
How can I pass a variable to $(shell) from inside a for loop? I can access the var outside of $(shell), but I don't know how to pass it to A_L